AI Pushes SSDs Into Compute: Nvidia’s CMX and NAND’s New Role
As AI models demand more context memory, SSDs are being reimagined as high-speed extensions to GPU memory, shifting NAND’s place in the tech stack.
This article originally appeared on Weijin Research on Sina on June 23, 2026. Original Chinese title: 「英伟达CMX与NAND的新故事 | 笔记」. It has been translated and adapted for an English-speaking audience.
AI is redrawing the boundary between memory and storage.
The NAND manufacturer SanDisk, which first proposed the concept of HBF (High Bandwidth Flash), has seen its market cap balloon more than 40-fold over the past year. Korean SSD controller maker FADU has “only” risen 9-fold, and is working hard to craft its own AI narrative.
Whether it’s HBF or SSDs, what’s really being repriced behind them is NAND. Just as HBM’s value ultimately rests on DRAM, NAND is now gaining a new strategic position in the future AI storage hierarchy.
FADU is firmly following Nvidia, believing that the CMX (Context Memory eXtension) architecture proposed by Jensen Huang at GTC earlier this year will push SSDs from their role as data warehouses toward “extended memory” that deeply participates in computation. If this judgment holds, then not only will direct demand for SSDs surge, but the core metrics that have guided SSD design for decades will need to be re-examined; at the very least, SSD design philosophy will begin to diverge based on actual workloads.
Nvidia’s introduction of CMX, like SanDisk’s HBF, aims to address the ever-expanding context caches in the agent era. This context exists in the form of KV Cache (key-value cache); otherwise, recomputing it for every conversation turn would not only increase response latency but also waste expensive GPU compute. Depending on the trade-off between access frequency and cache size, these KV Caches need to be placed at different tiers of the compute infrastructure.
As agents run continuously, KV Cache has gradually evolved from a session-level temporary byproduct into a durable asset worth keeping accessible long-term. By the Vera Rubin NVL72 era, it must find a location that is cheap enough, large enough, and fast enough. Existing HBM is already strained just holding model weights, and network storage latency struggles to meet inference demands, leaving room for a new memory tier.
Around this issue, the industry is forming two paths. KAIST (Korea Advanced Institute of Science and Technology) professor Kim Jung-ho believes in the HBF route, arguing that Nvidia proposed CMX only because it “has no teeth and can only chew gum,” and that eventually adopting HBF is “just a matter of time.” Meanwhile, FADU CTO Nam Yi-hyun believes that NAND’s issues in high-temperature environments and its inherent reliability problems make the commercialization prospects of HBF still highly uncertain; more importantly, without Nvidia’s push, it’s difficult for a new storage medium to build an ecosystem.
Since the start of this year, Nvidia has been rapidly building its own AI-native technology stack in the context space. Judging by the naming pattern, CMX is another brand family after CUDA-X and Spectrum-X. At CES earlier this year, it was still called ICMS (Inference Context Memory Storage), but two months later at GTC it was renamed CMX (Context Memory eXtension). Within Nvidia’s ecosystem, the larger architecture is STX (Storage Technology eXtension), which encompasses all context technologies including CMX.
Through CMX, KV Cache becomes a shared asset across the entire Pod. First, the host BlueField-4 on the GPU node virtualizes storage as a local NVMe (Non-Volatile Memory Express) device; but the actual data resides on a separate endpoint that has its own BlueField-4 and SSD pool. When a GPU issues a read request, the host BlueField-4 converts it into an RDMA (Remote Direct Memory Access) request and sends it over the network fabric. The endpoint BlueField-4 receives the request, reads the data from local NVMe SSDs, and then sends the data back. The result is delivered directly into GPU HBM via PCIe (Peripheral Component Interconnect Express) peer-to-peer. The host CPU and DRAM are not involved in this transfer at any point.
This means CMX achieves three goals simultaneously: near-DRAM latency via Spectrum-X; terabyte-scale per-GPU pod-level storage; and shared access across all GPUs. But it also means that SSDs designed for CMX are fundamentally different in design philosophy from traditional enterprise SSDs.
Under long-context and agent workloads, each GPU can generate tens of terabytes of KV Cache. Capacity must scale linearly with the number of GPUs, while being tightly constrained by rack power and space. During the decoding phase, KV Cache is predominantly read-heavy, with writes only during prefill and cache updates. This workload pattern is completely different from traditional databases or enterprise applications. In large-scale CMX deployments, SSDs themselves become a significant power consumer in the data center, and system-level tokens per watt (Token/W) will be directly affected by storage-layer efficiency.
In the past, enterprise SSDs served file systems and databases, with IOPS (input/output operations per second) as the core metric, pursuing massive 4KB random read/write capability and emphasizing cost per terabyte. The KV Cache in CMX, however, exhibits entirely different characteristics: large data blocks, predominantly sequential reads, and a focus on GB/s (how much data is moved per second) and cost per GB/s/W.
This is precisely the new opportunity that controller makers like FADU are seizing.